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Adaptive error protection for energy efficiency
2003
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)
With dramatic scaling in feature sizes, noise resilience is becoming one of the most important design parameters, similar to performance and energy efficiency. Noise resilience is particularly problematic in long on-chip buses of complex single chip systems such as on-chip multiprocessors. While one might opt to employ a very powerful error protection scheme, this may not be very energy efficient as noise behavior typically varies over time. In this paper, we propose an adaptive error
doi:10.1109/iccad.2003.159662
fatcat:2blun3ghmrbyvciuz7sswswtv4