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Coverage metrics for verification of concurrent SystemC designs using mutation testing
2010
2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)
Design verification has grown to dominate the cost of electronic system design; however, designs continue to be released with latent bugs. A verification test suite developed for a sequential program is not adequate for a concurrent program. A major problem with design verification of concurrent systems is the lack of good coverage metrics. Coverage metrics are heuristic measures of the exhaustiveness of a test suite. High coverage, in general, implies fewer bugs. SystemC is the most popular
doi:10.1109/hldvt.2010.5496659
dblp:conf/hldvt/SenA10
fatcat:jjcd6evcn5ahrh3yadhh2qjxja