A High-Speed Hardware Architecture for Universal Message Authentication Code
IEEE Journal on Selected Areas in Communications
We present an architecture level optimization technique called divide-and-concatenate based on two observations: (i) the area of a multiplier and associated data path decreases quadratically and their speeds increase gradually as their operand size is reduced. (ii) in universal hash functions and associated message authentication codes, two functions are equivalent if they have the same collision probability property . In the proposed approach we divide a 2w-bit data path (with collision
... th collision probability 2 -2w ) into two w-bit data paths (each with collision probability 2 -w ) and concatenate their results to construct an equivalent 2w-bit data path (with a collision probability 2 -2w ). We applied this technique on NH universal hash, a universal hash function that uses multiplications and additions. When compared to the straightforward 32-bit pipelined NH universal hash data path, the divide-and-concatenate approach yields a 94% increase in throughput with only 40% hardware overhead. The NH universal hash associated message authentication code UMAC architecture with collision probability 2 -32 that uses four equivalent 8-bit divide-and-concatenate NH universal hash data paths yields a throughput of 79.2 Gbps with only 3840 FPGA slices when implemented on a Xilinx Virtex II XC2VP7-7 Field Programmable Gate Array (FPGA) device.