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Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs
2006
Proceedings of the 16th ACM Great Lakes symposium on VLSI - GLSVLSI '06
This paper presents a minimum area, low-power driven clustering algorithm for coarse-grained, antifuse-based FPGAs under delay constraints. The algorithm accurately predicts logic replication caused by timing constraint during the low-power driven clustering. This technique reduces size of duplicated logic substantially, resulting in benefits in area, delay, and power dissipation. First, we build power-delay curves at nodes with the aid of the prediction algorithm. Next, we choose the best
doi:10.1145/1127908.1127929
dblp:conf/glvlsi/KangP06
fatcat:ckli23rbgzg3hktwadl7ojgzaa