Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs

Chang Woo Kang, Massoud Pedram
2006 Proceedings of the 16th ACM Great Lakes symposium on VLSI - GLSVLSI '06  
This paper presents a minimum area, low-power driven clustering algorithm for coarse-grained, antifuse-based FPGAs under delay constraints. The algorithm accurately predicts logic replication caused by timing constraint during the low-power driven clustering. This technique reduces size of duplicated logic substantially, resulting in benefits in area, delay, and power dissipation. First, we build power-delay curves at nodes with the aid of the prediction algorithm. Next, we choose the best
more » ... er starting from primary outputs moving backward in the circuit based on these curves. Experimental results show 16% and 20% reduction in dynamic and leakage power dissipation with 18% area reduction compared to the results of clustering without the replication prediction.
doi:10.1145/1127908.1127929 dblp:conf/glvlsi/KangP06 fatcat:ckli23rbgzg3hktwadl7ojgzaa