A Self-Testing Platform with a Foreground Digital Calibration Technique for SAR ADCs
This study presents a self-testing platform with a foreground digital calibration technique for successive approximation register (SAR) analog-to-digital converters (ADCs). A high-accuracy digital-to-analog converter (DAC) with digital control is used for the proposed self-testing platform to generate the sinusoidal test signal. This signal is then implemented using an Arduino board, and the clock signal is generated to test the ADCs. In addition, fast Fourier transform and recursive discrete
... urier transform (RDFT) processors are adopted for dynamic performance evaluation and calibration of the ADCs. The third harmonic distortion caused by the non-linearity of the track-and-hold circuit, the mismatch of the DAC capacitor array, and the direct current (DC) offset of the comparator can be calculated using the processors to improve the ADC performance. The advantages of the proposed platform include its low cost, high integration, and no need for an extra analogy compensation circuit to deal with calibration. In this work a 12 bit SAR ADC and an RDFT processor are used in the Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) 0.18 µm standard complementary metal-oxide-semiconductor (CMOS) process with a sampling rate of 18.75 kS/s to validate the proposed method. The measurement results show that the signal-to-noise and distortion ratio is 55.07 dB before calibration and 61.35 dB after calibration. An analog-to-digital converter (ADC) is an important component in various areas, such as communication and biomedical systems, among others. The performance limitations of the ADCs are mainly dominated by the static and dynamic non-linearity effects, which cause the harmonic distortion in the output power spectrum. These non-linearities slightly deteriorate the overall system performance, and also increase the sensitivity to the process variation and system interface noise because of the technology scaling into the nano-scale region. A calibration method is thus essential to ensure system quality [1, 2] . The successive approximation register (SAR) analog-to-digital converter (ADC) has the advantages of medium speed conversion and medium to high resolution. It is therefore very suitable for biomedical and communication systems. With regard to the implementation of most SAR ADCs, the performance should be maintained by the internal circuits, including the track-and-hold (T/H) circuit, the DAC capacitor array, and the comparator circuit. However, the non-linearity of the internal circuits always limits the performance of the ADCs. This is the reason why a calibration method is required to overcome this problem. In this paper we focus on the digital calibration method. For example, the lookup table or the state-space technique is a common calibration method for ADC error correction  . The correction in this approach is based on a table that uses pre-calculated values or the slope of the input signal. However, the drawback of this method is the requirement of a large memory size, thus consuming more areas. An equalization-based digitally calibrated method is proposed in Reference . The advantage of this is the reduction of both the ADC testing time and the convergence time. In addition, this paper utilizes the least mean squares (LMS) algorithm to correct and calibrate the ADC error, similar to that in Reference  . An internal redundancy dithering (IRD) technique is reported in Reference  . The IRD method based on bit-weight calibration employs a pseudorandom bit sequence to determine the threshold values. The method utilizes the LMS algorithm to calibrate the SAR ADC error. However, the main drawback of the approaches in References [5, 6] is that a high resolution ADC is required, which is impractical in actual implementation. A fast-Fourier transform (FFT)-based calibration method for pipelined ADC is reported to calibrate the capacitor mismatch and non-linearity error of the operational amplifier (OPAMP)  . However, the shortcoming of the FFT process is the consumption of more power because all frequency bins should be computed during the operation mode. Juan et al. proposed an RDFT-based calibration algorithm to overcome this problem , because the RDFT processor has the advantages of variable transform length, lower complexity, and less hardware cost. In this paper, we present a self-testing platform based on previous works [7, 8] to measure the ADC performance using the proposed testing stimulus and compensate for the error using a simplified digital calibration algorithm. A 12 bit SAR ADC and an RDFT processor are implemented in the TSMC 0.18 µm to verify the proposed platform. The output is analyzed using MATLAB (version 22.214.171.1244 (R2008a), The MathWorks, Natick, MA, USA, 2008), including the performance calculation and ADC calibration.