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To design an efficient integrated circuit in terms of Area, Power and speed is one of the challenging task in modern VLSI design field. In the past decade numbers of research have been carried out to optimize design based on area, speed and power utilization. In this paper performance analysis of different available adder architectures has been carried out and then we proposed a Heterogeneous architecture, which composed of four different sub adders (Ripple Carry, Carry Look Ahead, Carry Skipdoi:10.5120/8950-3132 fatcat:qnpkfafawfhh5cyshhbzdhfm6m