Flash Memory Scaling: From Material Selection to Performance Improvement

Tuo-Hung Hou, Jaegoo Lee, Jonathan T. Shaw, Edwin C. Kan
<span title="">2008</span> <i title="Cambridge University Press (CUP)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/fgrovy2offb63dlqiazaf7dkxq" style="color: black;">Materials Research Society Symposium Proceedings</a> </i> &nbsp;
Below the 65-nm technology node, scaling of Flash memory, NAND, NOR or embedded, needs smart and heterogeneous integration of materials in the entire device structure. In addition to maintaining retention, in the order of importance, we need to continuously make functional density (bits/cm 2 ) higher, cycling endurance longer, program/erase (P/E) voltage lower (negated by the read disturbance, multi-level possibility and noise margin), and P/E time faster (helped by inserting SRAM buffer at
more &raquo; ... em interface). From both theory and experiments, we will compare the advantages and disadvantages in various material choices in view of 3D electrostatics, quantum transport and CMOS process compatibility.
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