Most mobile devices support both 2D vector / 3D graphics using 3D graphics hardware, but this method is burdened by the CPU having to process curve tessellation with a large amount of calculation. This paper analyzes the graphics pipeline stages to design and validate a high performance / low-cost efficient hardware pipeline sharing structure that is suitable both for 2D vector graphics and 3D graphics applications. Simulate with real-world applications using 2D vector graphics APIs (OpenVG,

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... sh, SVG) and 3D graphics API (OpenGL ES) as inputs. Then, this paper designs and validates efficient 2D vector / 3D graphics core shared blocks such as low-cost antialiasing and numerical error approximation algorithms based on numerical calculation coverage, and gradients using matrix transformation and texture mapping. In this paper, a function call graph is extracted by profiling a function. This paper also analyzes the frequency, complexity, and association of functions in the full function call graph. This paper presents the optimization parameters such as shared block and bottleneck section analysis of the 2D vector/3D graphics pipeline stage, step delay prediction, etc., and drive parameters such as cache power mode switching criteria, prefetch decision and clock gating criteria. In order to maximize the performance, pipelines are arranged in parallel and pipeline bottleneck analysis is performed to maximize the pipeline throughput, which determines the number of pipeline stages and the step delay time.