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Currently, only Xilinx Field Programmable Gate Arrays (FPGAs) support Dynamic Partial Reconfiguration (DPR). While there is currently some Computer Aided Design (CAD) tool support for ISE-based DPR designs, none exists for microprocessor-based designs created in EDK. Creating DPR systems with the limited tool support currently available for ISE-based systems is already a challenging and complex process for novice DPR designers. These difficulties are severely compounded for potentialdoi:10.1109/fccm.2008.57 dblp:conf/fccm/ChenGSS08 fatcat:5fnrrc57kzhybgiqrrfl5lojcy