A Fast Emulation-Based NoC Prototyping Framework

Yana E. Krasteva, Francisco Criado, Eduardo de la Torre, Teresa Riesgo
2008 2008 International Conference on Reconfigurable Computing and FPGAs  
This paper presents an FPGA emulation-based fast Network on Chip (NoC) prototyping framework, called Dynamic Reconfigurable NoC (DRNoC) Emulation Platform. The main, distinguishing, characteristic of this approach is that design exploration does not requires re-synthesis, accelerating the process. For this aim, partial reconfiguration capabilities of some state of the art FPGAs have been developed and applied. The paper describes all the building elements of the proposed solution: the used
more » ... al reconfiguration approach, the design space exploration framework itself, and the data measuring system. Results and a use case are shown. RRM -Reconfigurable Routing Modules RNI -Reconfigurable Network Interface RE RE RNI RNI RE RNI RE RE RNI RNI RE RNI Routing Channels RRM RRM RRM RRM RRM RRM Fig. 1. DRNoC Architecture
doi:10.1109/reconfig.2008.74 dblp:conf/reconfig/KrastevaCTR08 fatcat:jm4uwu4qk5h4xbl5infdsk5fpe