This paper presents a regenerative frequency divider topology that provides two synchronous outputs of 1/N and (N −1)/N times the input frequency. This topology may lead to a saving in chip area and power consumption compared to cascaded divider chains trying to achieve the same division ratio. Design trade-offs are discussed following a theoretical treatment. A proof-of-concept divider with two synchronous outputs at 1/4 and 3/4 of the input frequency is designed in a 0.13 µm CMOS technology.

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... he implemented divider achieves a locking range of 5% around 4 GHz for an input power of 8 dBm and a DC power consumption of 5 mW from a 1 V supply.