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Migration in Hardware Transactional Memory on Asymmetric Multiprocessor
2021
IEEE Access
In this paper, a system is presented which implements transactions migration to an asymmetric multiprocessor in order to decrease the probability of conflicts and improve execution performance. Applications parallelization makes programming and testing much more difficult, so the goal is to avoid putting additional burden on a programmer. Therefore, the proposed solution should be fully implemented in hardware. In the asymmetric multiprocessor that is analyzed, all cores have the same
doi:10.1109/access.2021.3077539
fatcat:hddugctl5vfknpkml4tvi5i5ii