High temperature formed SiGe p-MOSFETs with good device characteristics

Y.H. Wu, A. Chin
2000 IEEE Electron Device Letters  
We have used a simple process to fabricate Si 0 3 Ge 0 7 /Si p-MOSFET's. The Si 0 3 Ge 0 7 is formed using deposited Ge followed by 950 C rapid thermal annealing and solid phase epitaxy that is process compatible with existing VLSI. Hole mobility of 250 cm 2 /Vs is obtained from Si 0 3 Ge 0 7 p-MOSFET that is two times higher than Si control devices and results in a consequent substantially higher current drive. The 228Å Si 0 3 Ge 0 7 thermal oxide grown at 1000 C has a high breakdown field of
more » ... breakdown field of 15 MV/cm, low interface trap density ( ) of 1 5 10 11 eV 1 cm 2 , and low oxide charge of 7 2 10 10 cm 2 . The source-drain junction leakage after implantation and 950 C RTA is also comparable with Si counterpart.
doi:10.1109/55.847377 fatcat:7x4r6lzqendptomyt4xgnwej6a