Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver

Kang-Yoon Lee, Seung-Wook Lee, Yido Koo, Hyoung-Ki Huh, Hee-Young Nam, Jeong-Woo Lee, Joonbae Park, Kyeongho Lee, Deog-Kyoon Jeong, Wonchan Kim
2003 IEEE Journal of Solid-State Circuits  
This paper presents a full-CMOS transmitter and receiver for 2.0-GHz wide-band code division multiple access with direct conversion mixers and a dc-offset cancellation scheme. The direct conversion scheme combined with a multiphase sampling fractional-prescaler alleviates the problems of the direct conversion transmitter and receiver. Digital gain control is merged into the baseband filters and variable-gain amplifiers to optimize the linearity of the system, reduce the noise, and improve the
more » ... nsitivity. Variable-gain amplifiers with dc-offset cancellation loop eliminate the dc-offset in each stage. The chip implemented in 0.35-m CMOS technology shows the experimental results of 6 dBm maximum output power with 38-dB adjacent channel power rejection ratio at 1.92 MHz, 50-dB dynamic range, and 363-mW power consumption in the transmitter. The receiver shows 115.4 dBm sensitivity, a 4.0-dB noise figure, and a dynamic range of 80-dB with 396-mW power consumption. Index Terms-Adjacent channel power rejection ratio (ACPR), dc-offset, direct conversion, fractionalprescaler, mixer, receiver, transmitter, wide-band code-division multiple access (WCDMA).
doi:10.1109/jssc.2002.806280 fatcat:b3awwy5lyrht3ibguf54k72g2u