Analog CMOS peak detect and hold circuits. Part 2. The two-phase offset-free and derandomizing configuration

Gianluigi De Geronimo, Paul O'Connor, Anand Kandasamy
2002 Nuclear Instruments and Methods in Physics Research Section A : Accelerators, Spectrometers, Detectors and Associated Equipment  
An analog CMOS peak detect and hold (PDH) circuit, which combines high speed and accuracy, rail-to-rail sensing and driving, low power, and buffering is presented. It is based on a configuration that cancels the major error sources of the classical CMOS PDH, including offset and common mode gain, by re-using the same amplifier for tracking, peak sensing, and output buffering. By virtue of its high absolute accuracy, two or more PDHs can be used in parallel to serve as a data-driven analog
more » ... for derandomization. The first experimental results on the new peak detector and derandomizer (PDD) circuit, fabricated in 0.35 mm CMOS technology, include a 0.2% absolute accuracy for pulses with 500 ns peaking time, 2.7 V linear input range, 3.3 mW power dissipation, 250 mV/s droop rate, and negligible dead time. The use of such a high performance analog PDD can greatly relax the requirements on the digitization in multi-channel systems. r
doi:10.1016/s0168-9002(01)02060-5 fatcat:jga2zsrtmnhpxdbwplbpbqylkm