Congestion estimation with buffer planning in floorplan design

Chiu-Wing Sham, Wai-Chiu Wong, E.R.Y. Young
Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition  
In this paper, we study and implement a routabilitydriven floorplanner with buffer block planning. It evaluates the routability of a floorplan by computing the probability that a net will pass through each particular location of a floorplan taken into account buffer locations and routing blockages. Experimental results show that our congestion model can optimize congestion and delay (by successful buffer insertions) of a circuits better with only a slight penalty in area.
doi:10.1109/date.2002.998375 dblp:conf/date/WongSY02 fatcat:sqght25645bgjemzkxyxpycr2m