A hardware and software monitor for high-level system-on-chip verification

M. El Shobaki, L. Lindh
Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design  
Verification of today's Systems-on-Chip (SoC) occur at low abstraction-levels, typically at register-transfer level (RTL). As the complexity of SoC designs grows, it is increasingly important to move verification to higher abstractionlevels. Hardware/software co-simulation is a step in this direction, but is not sufficient due to inaccurate processor models, and slow hardware simulation speeds. Systemlevel monitoring, commonly used for event-based software debugging, provides information about
more » ... ask scheduling events, inter-task communication and synchronisation, semaphores/resources, I/O interrupts, etc. We present MAMon 1 , a monitoring system that can both monitor the logic-level and the system-level in single/multiprocessor SoCs. A small hardware probe-unit is integrated in the SoC design and connects via a parallelport link to a host-based monitoring tool environment. The probe-unit collects all events in the target system in runtime, and timestamps them with a resolution of 1 s. The events are then stored in a database on the host for further processing. The paper will describe MAMon and how it works for software and hardware monitoring. The paper also describe how system-level monitoring can be achieved non-instrusively by using a hardware-based Real-Time Kernel.
doi:10.1109/isqed.2001.915206 dblp:conf/isqed/ShobakiL01 fatcat:x7in2je46vejfbonicf6w7cijm