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A hardware and software monitor for high-level system-on-chip verification
Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design
Verification of today's Systems-on-Chip (SoC) occur at low abstraction-levels, typically at register-transfer level (RTL). As the complexity of SoC designs grows, it is increasingly important to move verification to higher abstractionlevels. Hardware/software co-simulation is a step in this direction, but is not sufficient due to inaccurate processor models, and slow hardware simulation speeds. Systemlevel monitoring, commonly used for event-based software debugging, provides information about
doi:10.1109/isqed.2001.915206
dblp:conf/isqed/ShobakiL01
fatcat:x7in2je46vejfbonicf6w7cijm