Evaluation of parallel logic simulation using DVSIM

G. Meister
1996 Proceedings of HICSS-29: 29th Hawaii International Conference on System Sciences  
Parallel simulation is expected to speed up simulation run time in a significant way. This paper describes a framework that is used to evaluate the performance of parallel simulation algorithms. The framework's core is DVSIM, a parallel event-driven VHDL simulator. The framework provides several mechanisms to calculate sensible bases for speed-up calculation. Monitoring tools are employed to observe and to improve the algorithmic performance. A first implementation of DVSIM used a conservative
more » ... ynchronization method, but a Time Warp protocol has recently been completed. Influencing factors for speed-up such as partitioning and mapping methods are discussed. Experience shows that even with conservative synchronization schemes moderate speed-ups can be obtained for larger circuits. The speed-up values are compared to theoretically possible acceleration factors, and the reasons why these ideal maximum speed-up values can in general not be reached are explained.
doi:10.1109/hicss.1996.495487 dblp:conf/hicss/Meister96 fatcat:4r4jnx3jz5c5vigmw6ehuux3si