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Parallel simulation is expected to speed up simulation run time in a significant way. This paper describes a framework that is used to evaluate the performance of parallel simulation algorithms. The framework's core is DVSIM, a parallel event-driven VHDL simulator. The framework provides several mechanisms to calculate sensible bases for speed-up calculation. Monitoring tools are employed to observe and to improve the algorithmic performance. A first implementation of DVSIM used a conservativedoi:10.1109/hicss.1996.495487 dblp:conf/hicss/Meister96 fatcat:4r4jnx3jz5c5vigmw6ehuux3si