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EFFICIENT TIMING ELEMENT DESIGN FEATURING LOW POWER VLSI APPLICATIONS
2016
International Journal of Engineering and Technology
In this paper, we propose a novel Low-Power Dual dynamic node and edge triggered (DDNET) flip flop for Featuring Efficient low power applications. Several art of design techniques have been proposed to eliminate large capacitance in the precharge node of the conventional flip-flop, which drives separately by output pull-up, and pull down transistors. Though the pioneer designs which consumes much power and it has been overcome by our special handing techniques. The major aim of this work is to
doi:10.21817/ijet/2016/v8i4/160804409
fatcat:i3r4wgp3uvd5ng4eticugs52fq