PSP-Cache: A low-cost fault-tolerant cache memory architecture

Hamed Farbeh, Seyed Ghassem Miremadi
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014  
Cache memories constitute a large fraction of processor chip area and are highly vulnerable to soft errors caused by energetic particles. To protect these memories, most of the modern processors employ Error Detection Codes (EDCs) or Error Correction Codes (ECCs). EDCs/ECCs impose significant overheads in terms of area and energy; these overheads increase as a function of interleaving EDCs/ECCs to detect/correct multiple errors. This paper proposes a new cache architecture to minimize the area
more » ... nd energy overheads of EDCs/ECCs in setassociative L1-caches. Simulation results for a 4-way setassociative cache show that the proposed architecture reduces both the area and static power overheads of parity code by about 75% and the dynamic energy overhead by about 73% in comparison to conventional cache architecture. These reduction figures are about 68% and about 66%, respectively, for SEC-DED code. The above reductions are achieved without affecting the error coverage.
doi:10.7873/date.2014.177 dblp:conf/date/FarbehM14 fatcat:5jqzuzug5jgrdob5ux4e2d3cgm