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This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compressed form. However, decompression time causes a critical effect on the memory access time and variable-sized compressed blocks tend to increase the design complexity of the compressed cache architecture. This paper suggests several techniques to reduce the decompression overhead and to manage the compressed blocksdoi:10.1109/iccd.1999.808424 dblp:conf/iccd/LeeHK99 fatcat:aymlnuqw2bezfddjox3g53ltfu