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Average-Case Lower Bounds and Satisfiability Algorithms for Small Threshold Circuits

Ruiwen Chen, Rahul Santhanam, Srikanth Srinivasan, Marc Herbstritt

2016
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Computational Complexity Conference
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We show average-case lower bounds for explicit Boolean functions against bounded-depth threshold circuits with a superlinear number of wires. We show that for each integer d > 1, there is " d > 0 such that Parity has correlation at most 1/n ⌦(1) with depth-d threshold circuits which have at most n 1+" d wires, and the Generalized Andreev Function has correlation at most 1/2 n ⌦(1) with depth-d threshold circuits which have at most n 1+" d wires. Previously, only worst-case lower bounds in this
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... etting were known [22] . We use our ideas to make progress on several related questions. We give satisfiability algorithms beating brute force search for depth-d threshold circuits with a superlinear number of wires. These are the first such algorithms for depth greater than 2. We also show that Parity cannot be computed by polynomial-size AC 0 circuits with n o(1) general threshold gates. Previously no lower bound for Parity in this setting could handle more than log(n) gates. This result also implies subexponentialtime learning algorithms for AC 0 with n o(1) threshold gates under the uniform distribution. In addition, we give almost optimal bounds for the number of gates in a depth-d threshold circuit computing Parity on average, and show average-case lower bounds for threshold formulas of any depth. Our techniques include adaptive random restrictions, anti-concentration and the structural theory of linear threshold functions, and bounded-read Cherno↵ bounds. Electronic Colloquium on Computational Complexity, Report No. 191 (2015) p 5). Impagliazzo, Paturi, and Saks [22] showed a depth-d lower bound for general threshold circuits computing Parity: namely, that any such circuit must have wire complexity at least n 1+" d 2 where " 2 < " 1 . The proof of [22] proceeds by induction on the depth d. The main technical lemma shows that a circuit of depth d can be converted to a depth d 1 circuit of the same size by setting some of the input variables. The variables that are set are set in a random fashion, but not according to the uniform distribution. In fact, this distribution has statistical distance close to 1 from the uniform distribution and furthermore, depends on the circuit whose depth is being reduced. Therefore, it is unclear how to use this technique to prove a correlation bound with respect to the uniform distribution. In contrast, we are able to reduce the depth of the circuit by setting variables uniformly at random (though the variables that we restrict are sometimes chosen in a way that depends on the circuit), which yields the correlation bounds we want. Gate complexity. The aforementioned work of Paturi and Saks [34] also proved a near optimal⌦(n) lower bound on the number of gates in any depth-2 majority circuits computing Parity. Siu, Roychowdhury, and Kailath [45] considered majority circuits of bounded depth and small gate complexity. They showed that Parity can be computed by depth-d circuits with O(dn 1/(d 1) ) gates. Building on the ideas of [34], they also proved a near matching lower bound of⌦(dn 1/(d 1) ). Further, they also considered the problem of correlation bounds and showed that there exist depth-d majority circuits with O(dn 1/2(d 1) ) gates that compute Parity almost everywhere and that majority circuits of significantly smaller size have o(1) correlation with Parity (i.e. these circuits cannot compute Parity on more than a 1/2 + o(1) fraction of inputs; recall that 1/2 is trivial since a constant function computes Parity correctly on 1/2 of its inputs). Impagliazzo, Paturi, and Saks [22] extended the worst case lower bound to general threshold gates, where they proved a slightly weaker lower bound of ⌦(n 1/2(d 1) ). As discussed above, though, it is unclear how to use their technique to prove a correlation bound. Beigel [6] extended the result of Siu et al. to the setting of AC 0 augmented with a few majority gates. He showed that any subexponential-sized depth-d AC 0 circuit with significantly less than some k = n ⇥(1/d) majority gates has correlation o(1) with Parity. The techniques of all the above works with the exception of [22] were based on the fact majority gates can be well-approximated by lowdegree rational functions. However, this is not true for general threshold functions [44] and hence, these techniques do not carry over the case of general threshold gates. A lower bound technique that does carry over to the setting of general threshold gates is that of showing that the circuit class has low-degree polynomial sign-representations. Aspnes, Beigel, Furst and Rudich [3] used this idea to prove that AC 0 circuits augmented with a single general threshold output gate -we refer to these circuits as TAC 0 circuits as in [15] -of subexponential-size and constant-depth have correlation o(1) with Parity. More recently, Podolskii [36] used this technique along with a trick due to Beigel [6] to prove similar bounds for subexponential-sized AC 0 circuits augmented with general threshold gates. However, this trick incurs an exponential blow-up with the number of threshold gates and hence, in the setting of the Parity function, we cannot handle k > log n threshold gates. Another technique that has proved useful in handling general threshold gates is Communication Complexity, where the basic idea is to show that the circuit -perhaps after restricting some variables -has low communication complexity in some suitably defined communication model. We can then use results from communication complexity to infer lower bounds or correlation bounds. Nisan [29] used this technique to prove exponential correlation bounds for general threshold circuits (not necessarily even constant-depth) with n 1 ⌦(1) threshold gates. Using Beigel's trick and multiparty communication complexity bounds of Babai, Nisan and Szegedy [4], Lovett and Srinivasan [27] (see also [40, 17] ) proved exponential correlation bounds for any polynomial-sized AC 0 circuits augmented with up to n

doi:10.4230/lipics.ccc.2016.1
dblp:conf/coco/ChenSS16
fatcat:ju424xsqsrhhnalgoo3uq4x7ti