The first main result of this paper is the development of a low power threshold logic gate based on a capacitive input, charge recycling differential sense amplifier latch. The gate is shown to have very low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations. The second main result is the development of a novel, low depth, carry lookahead addition scheme. One such adder is also designed using the proposed gate. Section 5

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... proposed carry lookahead addition scheme is presented, and the designs for two novel CLAs are shown in Section 6. Finally a brief conclusion is given in Section 7.