Use of a CPLD in an Introductory Logic Circuits Course
2013 ASEE Annual Conference & Exposition Proceedings
In the 2011 Fall semester we successfully adopted a complex programmable logic device (CPLD) for use in our introductory logic circuits course at the University of Hartford. While the adoption of the corresponding CAD tools is an important element, we have been convinced, from the start of our research, that such a course must also be tangible to students. We feel that in such an introductory course, students must be aware that they are dealing with real circuits and that logic signals are
... ic signals are represented with physically measurable quantities. We found that in using a CPLD with a breadboard, the CPLD is identifiable to students, and that with modest wiring they constructed demonstrative circuits that they felt were satisfying and engaging. This paper outlines our more recent experience to further integrate our use of the CPLD in our introductory course. Given the potentially wide reaching impact on the curriculum, we are taking incremental steps, each with measurable goals. In the Fall 2012 semester, new lecture material involving hierarchy, propagation delay, and CPLD structure was developed. The tutorial was revised and new lab material was developed, to make use of these principles. In prior semesters, propagation delay and the more analog side of logic circuits were still presented in the context of TTL devices. We have developed material to introduce these same topics in the context of our CPLD module. We have students investigate CPLD propagation delay, first with a hands-on experience. Later in the lecture portion of the course, the internal structure of a CPLD is presented along with the device timing model The device timing model provides a means for students to better understand propagation delay within the device and how a device is actually implemented with a CPLD. Medium scale integration (MSI) devices such as decoders, multiplexers, and counters are important topics. TTL MSI devices each integrate into a single chip, the functionality provided by networks of small-scale integration (SSI) parts, such as gates and flip-flops. As with TTL MSI device integration, our CAD tools support a technique called hierarchy, in which students integrate lower level functionality, into their own MSI like symbols, which they can use in their own schematics. For our initial adoption of CPLDs, few changes were made to the actual course content. For our more recent experience, we developed new lecture and course content, and our tutorial material was expanded accordingly. Finally, we used student feedback to assess our results. In addition we are most concerned that our students still have meaningful experiences in the laboratory and lecture components of the course. In this paper we also present our future plans.