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A Unique Test Bench for Various System-on-a-Chip
2017
International Journal of Electrical and Computer Engineering (IJECE)
<p>This paper discusses a standard flow on how an automated test bench environment which is randomized with constraints can verify a SOC efficiently for its functionality and coverage. Today, in the time of multimillion gate ASICs, reusable intellectual property (IP), and system-on-a-chip (SoC) designs, verification consumes about 70 % of the design effort. Automation means a machine completes a task autonomously, quicker and with predictable results. Automation requires standard processes with
doi:10.11591/ijece.v7i6.pp3318-3322
fatcat:wl2ue663azgcbkqpfisdxpxqsy