Design methodology for construction of asynchronous pipelines with Handel-C

R.P. Self, M. Fleury, A.C. Downton
2003 IEE Proceedings - Software  
CSP channels are proposed as a means of developing high-level, asynchronous pipeline architectures over and above existing synchronous logic. Channel-based design allows hardware systems to be designed and constructed using top-down software engineering methods, which have not previously been available within hardware-software co-design. The intention is to enhance support for future large-scale co-designs. The design methodology and its performance implications are demonstrated through an
more » ... lar, pipelined design of the Karhunen-Loève Transform (KLT) algorithm, implemented using the Handel-C silicon compiler applied to dense FPGAs. 2
doi:10.1049/ip-sen:20030206 fatcat:ro5ekwlojfbwvm6fdilo67arr4