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Delay fault testing: choosing between random SIC and random MIC test sequences
Proceedings IEEE European Test Workshop
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. In this context, it has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when a high robust delay fault coverage is targeted. In this paper, we show that random SIC (RSIC) test sequences achieve a higher fault coverage than random MICdoi:10.1109/etw.2000.873772 dblp:conf/ets/VirazelDGLP00 fatcat:667brnd735e3jpo6r642y6bdzi