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Three dimensional integrated circuits (3D ICs) that stack multiple dies vertically using Through Silicon Vias (TSVs) have gained wide interests of the semiconductor industry. Fabricating these 3D ICs using wafer to wafer stacking has several advantages including: high throughput, high TSV density... However, one of the major challenges of the wafer to wafer stacking approach is the low compound yield. Various techniques have been presented in the literature to address this important problem.doi:10.1016/j.sbspro.2015.06.195 fatcat:gaa5hmh2fbgivihjyyhoqjemcm