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Mapping and optimization of the AVS video decoder on a high performance chip multiprocessor
2010
2010 IEEE International Conference on Multimedia and Expo
Modern multimedia workloads provide increased levels of quality and compression efficiency at the expense of substantially increased computational complexity. It is important to leverage the off-the-shelf emerging multi-core processor architectures and exploit all levels of parallelism of such workloads in order to achieve real time functionality at a reasonable cost. This paper presents the implementation, optimization and characterization of the AVS video decoder on Intel Core i7, a
doi:10.1109/icme.2010.5582558
dblp:conf/icmcs/KrommydasTAB10
fatcat:36fjeahcfvayngwne4id6t5orm