Design and Implementation of FIR Filter using Pipelined Distributed Arithmetic

Sanjay V. Chowdhary, Madhushree P., Madiha M. G., Pragati D., Rekha T.
2020 International Journal of Futures Research And Development  
This paper is about a pipelined architecture of reconfigurable FIR filter based on distribution arithmetic. The pipelining concepts will be introduced at the input side of the filter architecture. Due to this, the performance of FIR filter will increase in terms of speed. Here, Carry-Save Accumulation (CSA) is used to perform the shift/add accumulation. CSA reduces area complexity compared to Distributed Arithmetic (DA) -based partial product coefficient. The filter is simulated using Xilinx
more » ... ted using Xilinx 8.1i software and FPGA implementation performed using Xilinx Virtex2P.
doi:10.46625/ijfrd.2020.1103 fatcat:azu7bxai2vecpoks6imbsb5m2m