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Partial order reduction for scalable testing of systemC TLM designs
2008
Proceedings of the 45th annual conference on Design automation - DAC '08
A SystemC simulation kernel consists of a deterministic implementation of the scheduler, whose specification is nondeterministic. To leverage testing of a SystemC TLM design, we focus on automatically exploring all possible behaviors of the design for a given data input. We combine static and dynamic partial order reduction techniques with Sys-temC semantics to intelligently explore a subset of the possible traces, while still being provably sufficient for detecting deadlocks and safety
doi:10.1145/1391469.1391706
dblp:conf/dac/KunduGG08
fatcat:rpjqf2oenjdgvpxtzkphehsu7e