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A Decoupled KILO-Instruction Processor
The Twelfth International Symposium on High-Performance Computer Architecture, 2006.
Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elusive goal. Traditional processors are composed of structures that do not scale to large instruction windows because of timing and power constraints. However, the behavior of programs executed with large instruction windows gives rise to a natural and simple alternative to scaling. We characterize this phenomenon of
doi:10.1109/hpca.2006.1598112
dblp:conf/hpca/PericasCGJV06
fatcat:hadimequkjfhnbx3gayqhd7nem