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Design of Majority Logic Decoder for Error Detection and Correction in Memories
2017
IOSR Journal of VLSI and Signal processing
Due to augmenting integration densities, technology scaling and variation in parameters, the performance failures would possibly occur for every application. The memory applications are vulnerable to single event upsets and transient errors which may cause malfunctions. This paper deals with the idea of a totally distinctive fault detection and correction technique using EG-LDPC codes with the applying mainly targeted on reminiscences. The majority logic secret writing is used here, since it
doi:10.9790/4200-0703011926
fatcat:teyujcntknderpexl5r4cj2bk4