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In modern processors floating point divide operations often take 20 to 25 clock cycles, five times that of multiplication. Typically multiplicative algorithms with quadratic convergence are used for high-performance divide. A divide unit based on the multiplicative Newton-Raphson iteration is proposed. This divide unit utilizes the higher-order Newton-Raphson reciprocal approximation to compute the quotient fast, efficiently and with high throughput. The divide unit achieves fast execution bydoi:10.1109/dsd.2001.952327 dblp:conf/dsd/LiddicoatF01 fatcat:v5eraszkprdqdcbnjr4asin3xe