A New Design of a CMOS Comparator using 45nm Technology

Shruti Pancholi, Dr, R Meena
2015 IJISET-International Journal of Innovative Science, Engineering & Technology   unpublished
High speed comparator very much affects the overall performance of Pipelined Analog to Digital Converter (ADC) directly. A design of a CMOS comparator with 45nm technology and then simulated in Tanner software environment This paper presents the schematic design of a CMOS comparator with high speed low power dissipation and low noise. The simulation results show that this design can work with 1000MHz high speed clock frequency. Also the design has low power dissipation i.e. 0.25mw.