Architectures for block Toeplitz systems

Ilias Bouras, George-Othon Glentis, Nicholas Kalouptsidis
1996 Signal Processing  
In this paper efficient VLSI architectures of highly concurrent algorithms for the solution of block linear systems with Toeplitz or near-to-Toeplitz entries are presented. The main features of the proposed scheme are the use of scalar only operations, multiplications/divisions and additions, and the local communication which enables the development of wavefront array architecture. Both the mean squared error and the total squared error formulations are described and a variety of
more » ... are given. Zusammenfassung Kqvwords: Block Toeplitz matrices; Multichannel Schur algorithms; Parallel processing; VLSI implementation *Corresponding author. Fax: 301 72 28 981 0165-1684/96/$15.00 0 1996 Elsevier Science B.V. All rights reserved PZISO165-1684(96)00041-2 1. Bouras et al. / Signal Processing 51 (I 996) 167-I 90
doi:10.1016/0165-1684(96)00041-2 fatcat:gvlnfusymjgjha3jnkpvpglube