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2003 46th Midwest Symposium on Circuits and Systems
This paper addresses the use of architectural transformations for the low power realization of FIR filter and FFT algorithms on dedicated datapath architectures. We report significant power savings using the propose methodology. New low power arithmetic operators are used as basic modules. In FIR filter and FFT algorithms, 2's complement is a widely used encoding for signed operands. We use a new architecture for signed multiplication, which maintains the pure form of an array multiplier. Thisdoi:10.1109/mwscas.2003.1562584 fatcat:bvkx7ziwgvb6bmnfndk3nzkjbu