Security Analysis of Industrial Test Compression Schemes

Amitabh Das, Baris Ege, Santosh Ghosh, Lejla Batina, Ingrid Verbauwhede
2013 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Test compression is widely used for reducing test time and cost of a VLSI circuit. It is also claimed to provide security against scan based side-channel attacks. This paper pursues the legitimacy of this claim and presents scan attack vulnerabilities of test compression schemes used in commercial EDA tools. A publicly available AES design is used and test compression structures provided by Synopsys, Cadence and Mentor Graphics DfT tools are inserted into the design. Experimental results of the
more » ... ntal results of the differential scan attacks employed in this paper suggest that tools using X-masking and X-tolerance are vulnerable and leak information about the secret key. Differential scan attacks on these schemes have been demonstrated to have a best case success rate of 94.22% and 74.94% respectively for a random scan design. On the other hand, time compaction seems to be the strongest choice with the best case success rate of 3.55%. In addition, similar attacks are also performed on existing scan attack countermeasures proposed in literature, thus experimentally evaluating their practical security. Finally, a suitable countermeasure is proposed and compared to the previously proposed countermeasures.
doi:10.1109/tcad.2013.2274619 fatcat:gdate6muyjg7zizi7vjydr2ajq