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Test compression is widely used for reducing test time and cost of a VLSI circuit. It is also claimed to provide security against scan based side-channel attacks. This paper pursues the legitimacy of this claim and presents scan attack vulnerabilities of test compression schemes used in commercial EDA tools. A publicly available AES design is used and test compression structures provided by Synopsys, Cadence and Mentor Graphics DfT tools are inserted into the design. Experimental results of thedoi:10.1109/tcad.2013.2274619 fatcat:gdate6muyjg7zizi7vjydr2ajq