Resynthesis of combinational circuits for path count reduction and for path delay fault testability

A. Krstic, Kwang-Ting Cheng
Proceedings ED&TC European Design and Test Conference  
Path delay fault model is the most suitable model for detecting distributed manufacturing defects that can cause delay faults. However, the number of paths in a modern design can be extremely large and the path delay testability of many practical designs could be very low. In this paper we show how to resynthesize a combinational circuit in order to reduce the total number of paths. Our results show that it is possible to obtain circuits with a signi cant reduction in the number of paths while
more » ... ot increasing area and or delay of the longest sensitizable path in the circuit. Research on path delay testing shows that in many circuits a large portion of paths does not have a test that can guarantee detection of a delay fault. The path delay testability of a circuit would increase if the number of such paths is reduced. We show that addition of a small number of test points can help reducing the number of such paths in the given design.
doi:10.1109/edtc.1996.494345 dblp:conf/date/KrsticC96 fatcat:mmret2zc7fc3vb33s4ergp2ehu