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<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/4xfhwkuqw5f43mad6ock55mkeu" style="color: black;">2009 IEEE International High Level Design Validation and Test Workshop</a>
This work aims to address the well-known and acute challenge of functional validation for complex, contemporary microarchitectural circuit designs. We provide a new formal framework for algorithm level modelling-design modelling at a high abstraction level, focused exclusively on function and algorithms. The semantics of our models is based on Abstract State Machines with synchronous parallel execution, sequential execution, and nondeterminism. To express models we propose an executable,<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/hldvt.2009.5340168">doi:10.1109/hldvt.2009.5340168</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/hldvt/HannaM09.html">dblp:conf/hldvt/HannaM09</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/s7ugbceedjf4hgpvmtfpr3yyoe">fatcat:s7ugbceedjf4hgpvmtfpr3yyoe</a> </span>
more »... oriented Architecture Specification Language with rich data types and a well-defined formal semantics, based initially on Microsoft's AsmL. We describe an experimental framework for direct symbolic execution of models in this language, intended as a basis for both property and refinement verification, as well as design exploration. We explain and illustrate our approach through a case study, the modelling a simple µop scheduler and its refinement towards a design model for circuit implementation. We aim to show the utility of our language and symbolic execution framework for exploring microarchitectural algorithm and to validate designs using dynamic or formal techniques, yielding more productive convergence to high quality implementations. Abstract, yet sufficiently complete. All and only the algorithmically relevant features of the system should be represented. It need not be cycle-accurate or expressed at the bit level. Simple and concise, written in a language with meaning transparent to both system architects and designers. Precise, with a comprehensive and tractable formal semantics. This should be suitable to support a range of different formal verification technologies. Hardware-oriented. The model should provide a semantics suitable for the abstract characteristics of hardware-correctly modelling concurrency, synchronisation, clocking, hierarchy, and modular composition. Executable. The model can be run when encapsulated within a suitable test-bench and run-time environment.
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