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Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow
2007
Proceedings of the Second International Conference on Nano-Networks
Three-dimensional (3D) manufacturing technologies are viewed as promising solutions to the bandwidth bottlenecks in VLSI communication. At the architectural level, Networkson-chip (NoCs) have been proposed to address the complexity of interconnecting an ever-growing number of cores, memories and peripherals. NoCs are a promising choice for implementing scalable 3D interconnect architectures. However, the development of 3D NoCs is still at an early development stage. In this paper, we present a
doi:10.4108/icst.nanonet2007.2033
dblp:conf/nanonet/LoiAB07
fatcat:xrmlgkcfa5awlk6enj7afwhgw4