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A parallel pattern for iterative stencil + reduce
2016
Journal of Supercomputing
We advocate the Loop-of-stencil-reduce pattern as a means of simplifying the implementation of data-parallel programs on heterogeneous multi-core platforms. Loop-of-stencil-reduce is general enough to subsume map, reduce, map-reduce, stencil, stencil-reduce, and, crucially, their usage in a loop in both data-parallel and streaming applications, or a combination of both. The pattern makes it possible to deploy a single stencil computation kernel on different GPUs. We discuss the implementation
doi:10.1007/s11227-016-1871-z
fatcat:5zoh5a64lndidkmqeg6gnrkw6a