A digital PWM voltage mode controller integrated circuit (IC) for high-frequency dc-dc switching converters achieving virtually minimum possible, i.e. optimum, output voltage deviation to load transients is introduced. The IC is implemented with simple hardware, requiring small silicon area, and can operate as a single-phase or a two-phase controller. To minimize the area and eliminate known mode transition problems of the optimal response controllers, two novel blocks are combined. Namely, an

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... synchronous track-and-hold analogto-digital converter (ADC) and a "large-small" signal compensator are implemented. The ADC utilizes a pre-amplifier and only four comparators having approximately eight times smaller silicon area and power consumption than an equivalent windowed flash architecture. The "large-small" signal compensator consists of two parts, a digital PID minimizing small variations and a zero-current detection-based compensator suppressing large load transients. The large-signal compensator requires no extra calculations and has a low sensitivity to parameter variations. It utilizes a synchronization algorithm and the PID calculation results to obtain a bumpless mode transition and stable response to successive load transients. The IC occupying only 0.26 mm 2 silicon area is implemented in a CMOS 0.18µm process and its minimum deviation response is verified with a single and dual-phase 12 V-to-1.8 V, 500 kHz 60/120 W buck converter. I. This work of Laboratory for Power Management and Integrated SMPS is sponsored by NXP Semiconductors, Eindhoven, Netherlands. Figure 1 . A dual-phase buck converter controlled by the combined "large-small" signal digital controller.