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Maejo Int. J. Sci. Technol
This paper presents the modelling and analysis of the encapsulation process for three-dimensional (3D) stacking-chip package with through-silicon via (TSV) integration. The fluid-structure interaction of the 3D stacking-chip package encapsulation was modelled by finite volume and finite element codes, which were solved separately. The effect of the increase in the number of stacking chips was analysed. The visualisation of the 3D stacking-chip package encapsulation process was presented atfatcat:jlb7pg4nvraxpltjhlb7ivjute