This paper presents the modelling and analysis of the encapsulation process for three-dimensional (3D) stacking-chip package with through-silicon via (TSV) integration. The fluid-structure interaction of the 3D stacking-chip package encapsulation was modelled by finite volume and finite element codes, which were solved separately. The effect of the increase in the number of stacking chips was analysed. The visualisation of the 3D stacking-chip package encapsulation process was presented at

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... rent filling times. The void formation around the stacking chips was identified for each case. The displacement and von Mises stress for the copper through-silicon vias were determined. The use of designed inlet-outlet heights in the integrated circuit package maintained the filling time of the encapsulation process and reduced the void of the packages as the number of stacking chips increased. The encapsulation model facilitated a clear visualisation and enhanced fundamental understanding of the design of a 3D integrated circuit encapsulation. The proposed analysis is expected to be a reference and guide in the design and improvement of 3D integration packages.