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BulletProof: A Defect~Tolerant CMP Switch Architecture
The Twelfth International Symposium on High-Performance Computer Architecture, 2006.
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transient errors, and transistor wear-out. Unless these challenges are addressed, computer vendors can expect low yields and short mean-timesto-failure. In this paper, we examine the challenges of designing complex computing systems in the presence of transient and permanent faults. We select one small aspect of a typical
doi:10.1109/hpca.2006.1598108
dblp:conf/hpca/ConstantinidesPBZBMAO06
fatcat:zoigoavtl5g55pjhras3t2etzq