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Automatic verification of sequential circuit designs
1992
Philosophical Transactions of the Royal Society of London Series A Physical and Engineering Sciences
Temporal logic model checking is a method for automatically deciding if a sequential circuit satisfies its specifications. In this approach, the circuit is modelled as a state transition system, and specifications are given by temporal logic formulas. Efficient search algorithms are used to determine if the specifications are satisfied or not. The procedure has been used successfully in the past to find subtle errors in a number of non-trivial circuit designs. Recently, the size of the circuits
doi:10.1098/rsta.1992.0028
fatcat:pkrj3pof5jcjhn5uvgiishj6ay