Front-end amplifier of low-noise and tunable BW/gain for portable biomedical signal acquisition

Chun-Chieh Huang, Shao-Hang Hung, Jen-Feng Chung, Lan-Da Van, Chin-Teng Lin
2008 2008 IEEE International Symposium on Circuits and Systems  
We proposed a novel analog circuit design which is suitable for various biomedical signal acquisitions. In addition to the consideration of low power and low noise, the analog front-end integrated circuit (AFEIC) is presented with design of high common-mode rejection ratio (CMRR) and high power supply ripple rejection ratio (PSRR). It has not only reduced the number of outer components, and enhances a better signal-to-noise ratio (SNR). The chip includes a current-balancing instrumentation
more » ... fier, switched-capacitor filter, non-overlapping clock generator, and a programmable gain amplifier (PGA). It was fabricated by TSMC 0.35 µm CMOS 2P4M standard process, with CMRR 155 dB CMRR, 131 dB of PSRR+, and 127 dB of PSRR-at 50 Hz. The power consumption is about 142.4 µW under ±1.5V supply.
doi:10.1109/iscas.2008.4542018 dblp:conf/iscas/HuangHCVL08 fatcat:kadf75igg5e2peube2ou7wn4ka