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Instruction set simulators are critical tools for the exploration and validation of new programmable architectures. Due to increasing complexity of the architectures and timeto-market pressure, performance is the most important feature of an instruction-set simulator. Interpretive simulators are flexible but slow, whereas compiled simulators deliver speed at the cost of flexibility. This paper presents a novel technique for generation of fast instruction-set simulators that combines the benefitdoi:10.1145/775832.776026 dblp:conf/dac/ReshadiMD03 fatcat:nlxudj6tcva2dkandc7ponu7kq