Multiplier is one of the important elements in most of the digital processing system such as FIR filters, digital signal processors and microprocessors etc. The two important parameters of a multiplier design are its area and speed that are inversely proportional. The speed of a system depends on how a faster an arithmetic operations are performed. The main problem in designing of VLSI circuits are high power consumption, large area utilization and delay which affect the speed of the

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... and also results in power dissipation. In general, speed and power are the two essential factors in VLSI design. For solving the issues, a new architecture has been design. In proposed design, two multipliers are used modified booth multiplier and Wallace tree multiplier with Ripple carry adder. Modified booth multiplier is used to reduce number of partial products whereas Wallace tree multiplier is used for fast addition and finally, ripple carry adder is used for final accumulation. This paper presents study of different booth algorithm and design of multiplier by using modified booth algorithm (MBA). Multiplier circuit will be design using Verilog and simulated using Xilinx ISE Simulator. Keyword:-Modified booth algorithm, Wallace tree, and ripple carry adder