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Novel modulo 2n+1 subtractors
2009 16th International Conference on Digital Signal Processing
Novel architectures for designing modulo 2 n +1 subtractors are introduced, for both the normal and the diminished-one number representation of the operands. Zero-handling is also considered in the diminished-one operand representation case. The modulo 2 n +1 subtractors for operands in the normal representation that are proposed are shown to be more efficient in area, delay and power dissipation than the currently most efficient ones. The proposed diminished-one modulo 2 n +1 subtractors offerdoi:10.1109/icdsp.2009.5201052 fatcat:egzrpk6ejndinhjh7mn6zrzg5a